A problem to be solved for the high integration of semiconductor devices is a short-channel effect caused with reduction in gate linewidth in a transistor. Recently, Samsung Electronics Co., Ltd. suggested a recess channel array transistor (R-CAT) to overcome this problem.
A method of fabricating a DRAM device using an R-CAT process will now be described with reference to FIG. 1, which shows a portion of a cell array region of the DRAM device. FIG. 2A and FIG. 2B are cross-sectional views taken along lines I-I′ and II-II′ of FIG. 1, respectively.
Referring to FIG. 1, FIG. 2A, and FIG. 2B, device isolation layers 10 are formed in a predetermined region of a semiconductor substrate 1 to define active regions 20. Conventionally, formation of each device isolation layer 10 is done using a shallow trench isolation (STI) technique. Mask patterns 30 are formed on a resultant structure where the device isolation layer 10 is formed. The mask patterns 30 expose top surfaces of the active regions 20 and the device isolation layer 10. In a process for fabricating a DRAM device, three mask patterns 30 are formed on the respective active regions 20 to expose the top surface of each active region 20 at two spots (between three mask patterns), as illustrated in FIG. 1.
With reference to FIG. 2A, using the mask patterns as etch masks, the exposed active regions 20 are anisotropically dry-etched to form a recess channel region 40. In the case of the foregoing DRAM device, two recess channel regions 40 are formed in the respective active regions 20. Formation of the recess channel region 40 is followed by a typical gate forming process (not shown) including sequentially forming a gate insulation layer and a gate conductive layer.
In a top surface of the semiconductor substrate 1, the center of the recess region 40 is less etched than a boundary portion 9 (FIG. 1) contacting the device isolation layer 10 during the etch for forming the recess channel region 40. Thus, a bottom surface of the recess channel region 40 is gradually elevated to contact a sidewall of the device isolation layer 10. As a result, an upwardly sharp active-region protrusion 99 (FIG. 2A) is formed at the boundary portion 9 (FIG. 1) of the device isolation layer 10 and the recess channel region 40.
Due to a protruding shape of the active-region protrusion 99, an electric field may concentrate at the active-region protrusion 99 when a voltage is applied to the active region. Since the concentration of the electric field may result in leakage current caused by a tunneling phenomenon, the active-region protrusion 99 must be removed prior to formation of the gate insulation layer. The removal of the active-region protrusion 99 is conventionally done using chemical dry etching (CDE). However, the CDE must be performed for each wafer individually, which may result in poor processing efficiency.
As illustrated in FIG. 1 and FIG. 2B, the mask patterns 30 also expose a top surface of the device isolation layer 10. Thus, during the etch for forming the recess channel region 40, the top surface of the device isolation layer 10 is etched to form a recess or gap area 45 (FIG. 2B). However, the gap area 45 may have a portion 88 that extends to the vicinity of an active region during the removal of the active-region protrusion 99. If the gap region 45 extends to the vicinity of the active region, an electric short may occur between the active region 20 and the gate conductive layer. For this reason, there is a requirement to remove the active-region protrusion 99 while reducing the depth of a recess (i.e., the gap region 45) of the device isolation layer 10.